1. Field of the Invention
The present invention relates to a microinstruction executing system and more specifically to a high speed microinstruction executing system which can reduce the execution processing time of a microprocessor.
2. Description of the Prior Art
FIG. 1(A) shows an example of a prior-art microinstruction executing system incorporated in a microprocessor. The system comprises a ROM 1, a sequencer 3, a microinstruction register 5, a decoder 9, a general register 11, an arithmetic unit 7, a D (destination) bus 13, a S (source) bus 15, a latch 17, and a timing generator 19.
The ROM 1 stores microprograms composed of microinstructions for executing machine language instructions given externally. These microinstructions stored in this ROM 1 are read in sequence under control of a sequencer 3 and then held temporarily in a microinstruction (MIR) register 5. The MIR register 5 includes an operation (op) field for controlling operations of an arithmetic unit (ALU) 7, a destination control (DC) field for designating a register which holds destination data operated on by the ALU 7, and a source control (SC) field for designating a register which holds source data for the succeeding calculation operation.
The microinstructions held in the MIR register 5 are decoded by the decoder 9, and control signals from each field of the MIR register 5 are generated to control the corresponding parts of the system. That is, the control signals from the OP field are supplied to the ALU 7, and control signals from the DC field and the SC field are supplied to the general register 11.
The general register 11 is composed of plural registers which store various data such as source data, destination data, etc. These data are written in the general register 11 via the D (destination) bus 13, and read from the general register 11 via the D bus 13 and the S (source) bus 15.
The ALU 7 executes various arithmetic operations between data supplied from the general register 11 via the S bus 15 and data latched in a latch register 17 from the general register 11 via the D bus 13. The results of these operations are transferred to the general register 11 again via the D bus 13 and stored therein.
A timing generator 19 generates timing signals for controlling the data transfer timing among the general register 11, the latch register 17, and the ALU 7. These timing signals are generated by dividing a single machine clock in accordance with data transfer timings.
In the above-mentioned configuration, execution processing of microinstructions such as "ADD, GR0, GR1" (add a value (GR0) of a register GR0 and a value (GR1) of a register GR1, and store the result of addition (ALU) in the register GR0) will be described with reference to FIG. 1(B).
When the above-mentioned microinstruction is read from the ROM 1, the microinstruction is decoded by the decoder 9, so that data of the register GR0 is read out to the D bus 13 and data of the register GR1 is read out to the S bus 15. As by the timing chart shown in FIG. 1(B), these operations are executed during a duration .phi..sub.1 obtained by dividing a single machine clock.
The data on the D bus 13 and the S bus 15 are supplied to the ALU 7 during a duration .phi..sub.2 shown in FIG. 1(B) for addition. That is, the data transfer processing from the register GR0 and the register GR1 and the data addition processing are executed during a duration To=(.phi..sub.1 +.phi..sub.2) shown in FIG. 1(B).
The result of the ALU 7 operation is put on the D bus 13; data on the D bus 13 is latched by the latch register 17; and the result of addition on the D bus 13 is stored in the register GR0 during a duration .phi..sub.3 shown in FIG. 1(B).
In the prior-art microinstruction executing system, although the execution processing of the microinstruction is implemented as described above, the execution time (one machine clock) for one microinstruction in the system shown in FIG. 1(A) is divided into the read (transfer) time .phi..sub.1 for the two data to be transferred from the registers to the ALU, the addition operation time .phi..sub.2 the ALU 7, and the storing (transfer) time .phi..sub.3 of the result of addition in the register, thus taking a long instruction execution time.
Further, since a series of operations of data read, addition operation, addition result transfer and store are executed in response to timing signals produced by dividing a machine clock, there exist various problems in that the control operations are complicated and a timing generator 19 for generating timing signals is required, thus complicating the system configuration.